The subject invention is directed generally to mesh processing arrays, and is more specifically directed to a one-bit mesh processor and a mesh processor array architecture that utilizes the one-bit processor.
A mesh processing array is a form of parallel processing wherein generally identical mesh processors are interconnected in a grid-like fashion, for example, in rows and columns. Each processor is coupled to processors adjacent thereto (e.g. , a maximum of four in a row and column configuration) with data input/outputs being provided via the processors on the periphery of the grid array. Commonly, the processors receive control signals (e.g. , control words or op-codes) in parallel and are clocked in parallel.
Examples of known mesh processor arrays include the NCR 45CG72 array processor and the AMT DAP array process sor.
An important consideration with some known mesh processors arrays is the allocation of dedicated storage (memory) per processor cell which is typically not sufficiently large (e.g. , 128 bits) except for few applications. Greater memory requirements are met by the use of a virtual processor cell comprising a plurality of real processor cells, which generally results in wasted memory since the virtual cell memory is an integral multiple of the real cell memory size.
A further consideration with known mesh processor arrays is the use of special function units or other special hardware which is utilized only part of the time, and therefore is not efficiently utilized.
As a result of large memories and special hardware, known processor arrays are quite large and cannot be operated at high clock rates.